Electronic Military & Defense magazine was developed for engineers, program managers, project managers, and those involved in the design and development of electronic and electro-optic systems for military, defense, and aerospace applications.
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Technology Tuning Image And Sensor Systems To Military Functions Using FPGAs The use of high-level language (HLL) techniques makes it easier to tune FPGAs for specific projects. By Brian Durwood, Ed Trexel, and Ross Snider S everal trends at the "bleeding edge" of image and sensor processing are leading software developers to consider offloading compute-bound processes to field-programmable gate arrays (FPGAs). FPGAs are, admittedly, a bit harder to work with and certainly more expensive than CPUs or GPUs. So, what makes them worth- while? A few things: Foremost, users have the ability to architect (or "tune") the majority of the FPGA logic primarily toward the specific process being accelerated. Second, users can combine all functions on a single device (a system-on-chip, or SoC). Third, users can reduce power by extensive parallelization of processes to run at slower clock speeds and at lower equivalent power. Finally, FPGA processing time can be deterministically counted in clock cycles, as compared to the indeterminate behavior of operating systems. However, achieving these outcomes is not easy. Many developers have used FPGAs or programmable logic as a controller or "glue" device. VHDL and Verilog were good for that, but offloading processing usually involves porting algorithmic logic originally described in an HLL, such as C or OpenCL. The usage wherein one configures an FPGA as a super processor for a specific application sometimes is called an ASSP (application specific standard product). But the compiler/synthesis path to this usage is, to some extent, a black box. The software developer will get great results if the designer stays mid-stream in design aggres- siveness. At the edges, though, where high-performance computing (HPC) lives, there are pitfalls. Using algorith- mic design entry to propagate logic throughout an FPGA can trigger hidden resource limits, trip over-integration issues, or bog down due to input/output (I/O) issues. This article describes optimizations that complement certain design goals, and it explains methodologies for reducing pitfalls, such as including HPC-oriented tool flows or investing in board support packages to abstract away many of the hardware interfaces. The primary design types in this article are sensor/camera driven. The proliferation of streams of data, flowing from ever-higher resolution sensors and cameras, combined with the increasing array size of multi-sensor systems, is creating compute-bound challenges for these system architects. One common strategy is to pre- process or offload the CPU to an FPGA(s). The constant improvement in HLL interfaces and design tools for FPGA makes this option more accessible to software develop- ers, rendering unnecessary much of the hardware-level design that would have been required just five years ago. The authors see the emerging confluence of HLLs used to design FPGA hardware and customizable pre-processors as introducing new capabilities to optimize logic resources for very narrow or custom targets. The optimization may focus on applying bandwidth, resolution, frame rate, or another custom value to a specific task. There are trade-offs to using HLLs over a hardware description language (HDL), though. HLLs, by design, abstract away the specifics of the underlying hardware con- taining different memory topologies and types, along with different computational resources. This abstraction does limit the flexibility of the design in terms of how that underlying hardware can be modified to fit the algorithm being embed- ded. However, what is lost in flexibility is made up for in ease of implementation, provided there is a match that can easily be made between an HLL and the specific hardware architecture. There are two general hardware architectures that lend themselves to an HLL design abstraction for FPGAs. The first one is the coprocessor design approach, which fits with the HPC view where compute-intensive algorithms are imple- mented in the FPGA. This typically takes the form of an FPGA card that has been plugged into a PC, where the algorithm then is partitioned into the part that best runs on a CPU and the parallel part that can be implemented in the FPGA fabric. Amdahl's law inserts itself in this scenario because, if the time Electronic Military & Defense Annual Resource, 5th Edition 24 Figure 1: Diagram of a "bump-in-the-wire" approach to stream processing