Electronic Military & Defense Annual Resource

5th Edition

Electronic Military & Defense magazine was developed for engineers, program managers, project managers, and those involved in the design and development of electronic and electro-optic systems for military, defense, and aerospace applications.

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"Truck Spotting" "Truck spotting" refers to the system of trying to find a spe- cific object type, and it may be architected to bias logic use toward a polar FFT. Jokingly referred to as "frog vision," it biases logic toward one object type in multiple aspects. In the same way that a frog's brain/vision is biased toward rapid reaction to its prey, satellite imaging can be biased toward spotting a particular object, regardless of the angle of view. For example, a missile could be richly defined by multiple possible aspect ratios using polar FFT logic, which can com- pensate for head-on, angled, or side views — in which that missile could appear as a dot, a slash with a curved tail, or a streaming line with a tail. ASSP Model In the SoC universe, there is a re-emergence of program- mable devices as ASSPs. The original programmable logic devices, using tools like PALASM, CUPL, and ABEL, replaced multiple TTL devices. One of this article's authors (Durwood) helped launch ABEL, and he recalls that many early sales were applied to writing address decoders. Now, the industry has come full circle, and the new generation of lower-cost FPGAs is being marketed as ASSPs. In this function, the devices are self-contained — often as SoCs with embedded processors — and become a callable component that can be reused between several programs. Programmable Network Interface Cards (NICs) NICs strive to keep protocols (control and video streaming) on CPU and make FPGA look like a pipe, decoding UDP (user datagram protocol) and steering it to DMA (direct mem- ory access), for example. In this configuration, a BSP layer automates the drivers to the board's hardware resources, and the focus of design is reduced to figuring out how to opti- mize the OpenCL Kernels inserted in the information stream. PCI Express (PCIe) currently is the favored host interface in these applications. HLLs = Speed HLLs accelerate development, dramatically speed up itera- tion, and buy "insurance" for future FPGAs. Increased emphasis on experimenting with partitioning and architec- ture, toward minimizing I/O and appropriately concentrat- ing logic resources, has caused increased interest in HLLs. OpenCL and C tools have emerged that make FPGA design tools less "career limiting" (i.e., less frequently relegated to just one niche of digital design). In this C design tool flow: • The software prototyping may begin on CPU ¤ Profiling identifies bottlenecks ¤ Engineer offloads appropriate portions to parallel processing in FPGA ¤ HLL tool options for FPGA: C, OpenCL, Heterogeneous (mixed with VHDL or Verilog) ¤ Board support integration increases accessibility to software developers • Function types bias majority of logic resources, often honed iteratively, toward: ¤ Narrow spectrum ¤ Frame rate biased ¤ Resolution biased ¤ Unique aspect ratios ¤ Concentrated processing on one feature, color band, or shape Conclusions The authors are beginning to look at the infrastructure impact of 2016 higher-resolution cameras and the emerging com- mercial off-the-shelf (COTS) 40- and 100-gbps boards. We generally expect available sensor information to outpace the available bandwidth, putting pressure on clever preprocess- ing, encryption, and compression schemes. To succeed in this environment, we recommend: • Figure out what's important to you: resolution, power, bandwidth, encryption, etc. • Bias logic resources accordingly. • Keep as much as possible in HLL. • Maximize what can occur on a single device and minimize data movement off device, particularly to memory. Technology 30 Figure 4: Programmable, aka software-defined, network interface cards make it easy for an engineer to partition logic between CPU and FPGA and to address the I/O and hardware elements of the card from an HLL, like C. Electronic Military & Defense Annual Resource, 5th Edition Brian Durwood worked on Data I/O's ABEL project with the advent of programmable logic and as a VP at Tektronix before co-founding Impulse Accelerated, which provides high-performance FPGAs, design- to-spec, for commercial and government image processing projects in the U.S. and abroad. Durwood is a graduate of Brown University and the University of Pennsylvania's Wharton School of Business. Ed Trexel runs engineering at Impulse Accelerated, where he directs the vision for future tools. Prior to Impulse, Trexel served as senior staff hardware/software development engineer at Polycom. He holds a BSEE/ BSCS in electrical engineering from Colorado State University. Dr. Ross Snider is an associate professor in the Electrical and Computer Engineering Department at Montana State University – Bozeman. Snider's research spans signal processing, machine learning, and embedding real-time algorithms in field-programmable gate arrays (FPGAs).

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