Electronic Military & Defense magazine was developed for engineers, program managers, project managers, and those involved in the design and development of electronic and electro-optic systems for military, defense, and aerospace applications.
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Criterion #3 typically was analyzed by a supply chain team, which identified capable suppliers based on technical and business aspects. But, early analysis of criteria #1 and #2 are the domain of the engineering team. With single- die solutions, this came down to performing synthesis and place and route (P&R;) PF experiments to determine die size and performance/power. Normally, teams would run many overnight tests on server farms and then review the results over the following days to identify viable scripts and floor plans. The larger the server farms, the more experiments could be run over a shorter time period. This PF methodology allowed engineering teams to quickly home in on optimized single-chip silicon solutions. Nirvana Ends: Fin Field Effect Transistors (FinFETs), Double/Triple Patterning, Extreme Ultraviolet Lithography (EUV) As silicon device engineering continued to achieve denser transistors and interconnect, new physical phenomena required additional changes for silicon scaling, while still producing yieldable die. But each change added significant complexity and cost to the design effort (FinFETS) or manufacturing costs (double/ triple patterning, EUV, etc.). As new phenomena are discovered, these costs will continue to escalate. Recent articles 1,2 have shown development costs accelerating with each denser process node (28nm: $30M, 14nm: $80M, 10nm: $120M, and 7nm: $271M). With these exorbitant costs, product developers can no longer rely on the "easy" solution — migrate to the densest node available. Today, product architects and developers must look at alternatives that meet their criteria and are constructed from heterogeneous solutions. The product solution space has exploded from two-dimensional (homogeneous silicon) to two+ dimensions (heterogeneous). In effect, Pandora's box has been opened by escalating costs. Long-established methods and guidelines must be altered for new complexities, and PF's role must change. Rather than focusing solely on homogeneous silicon, PF must expand to include other components (i.e., additional dimensions) — packages, interposers, balls/bumps, underfill, wire bonds, RDL, uVIAs, and/ or TSVs, etc. — and determine how they might be combined into workable solutions. This is analogous to simulating a city's infrastructure (roads and signaling) to determine how quickly a driver can get from point A to point B during various times of the day. Synthesis and P&R; scripts focus on optimizing local areas, while true performance relies on overall infrastructure (system). Controlling Pandora's Box: A Designer's Perspective Consider a situation I experienced: A company is ready to send a silicon chip for manufacturing. A recently hired, experienced signal and power integrity (SI/PI) engineer feels the current design implementation is insufficient for noise shielding, but the development and implementation teams already are on their next projects, leaving few resources available. The engineer's challenge: Quickly prove issues exist and, if the veracity of the engineer's concerns is proven, quickly determine an improved solution. Many would wonder how such a scenario could happen so late in the development stage, but this happens more frequently than many will admit: Last-minute functional changes or new verification tests uncover issues that have existed for months. At this point, not only is time of the essence, but also many physical and financial constraints have solidified and must be satisfied. A new solution must fit in the same physical location, with the same interconnect, same number of metal layers (cost), etc. 36 Trends Electronic Military & Defense Annual Resource, 6th Edition Figure 1: Redistribution layer (RDL) and different return paths Figure Figure 2: Near End and Far End cross talk 2: Figure 2: Near End and Far End cross talk Near Figure 2: Near End and Far End cross talk End Figure 2: Near End and Far End cross talk and Figure 2: Near End and Far End cross talk Far Figure 2: Near End and Far End cross talk End Figure 2: Near End and Far End cross talk cross talk Figure 2: Near End and Far End cross talk