Electronic Military & Defense magazine was developed for engineers, program managers, project managers, and those involved in the design and development of electronic and electro-optic systems for military, defense, and aerospace applications.
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Technology Enabling Larger Phased-Array Radars With JESD204B The new JESD204B high-speed digital interface shows promise of simplifying the digital interconnects between the data converters and processor in phased-array radar systems. By Thomas Neu I n an effort to keep up with evolving threats over the differential signaling), require sophisticated methods past 50 years, conventional radar with mechanically for large-scale sample alignment and timing calibration. scanning antennas have been largely replaced with phased-array systems. The benefits of the phasedTraditional Parallel Digital Interface array, or active electronically scanned-array (AESA), radar The current generation of phased-array radars still uses range from being able to use beamforming for improved data converters with a proven parallel LVDS or DDR (double data rate) LVDS interface, which provides the range and better target accuracy to the elimination of digital data and a bit clock to latch in the data. The trace hydraulics (and their potential failure). It also allows length of the data bus lines has to be matched carefully tracking multiple targets simultaneously while continuing to satisfy the bit clock setup and hold times. Often system to search, as the array can be configured to steer multiple designers avoid using a common clock to latch in data beams. By replacing the single, high-power transmitter of multiple standalone analog-to-digital converter (ADC) (exciter) and receiver with a large array of smaller, channels into the processor. This is because, in addition lower-power elements, the most common single point of to the routing challenge of matching trace lengths across failure is eliminated — similar to replacing a single highADCs, the data converter's output timing also includes powered lightbulb with smaller-sized LEDs. a variable propagation delay that depends on process, Modern phased-array radars consist of hundreds to tens voltage, and temperature, and, thus, varies from part to of thousands of radiating elements, where the phase of part. Alternately, dual or quad ADCs are preferred, as all each transmitter element can be independently controlled. the ADCs on the same die have the same propagation In this way, beams can be formed by adjusting the phase delay. and power of each element, and the beam direction Consequently, using different bit clocks results in can be controlled using constructive or destructive phase differences across the various ADC channels, interference of multiple elements. Each array element which need to be absorbed also includes a receiver, which with a FIFO (first in, first out) collects the energy reflected from the target and is phasein the receiver. However, locked to the transmitter. since the output data of the individual ADCs does not come As the array size increases with an inherent "time stamp" to identify smaller targets that would simplify aligning in cluttered environments the data across the phased with better resolution array, the exact synchronization and accuracy, so does the may require high orders of challenge of synchronizing all sophistication. This may set a the individual elements. The practical limitation on the size accurate phase control of each of the phased array in terms of single element and the clock number of elements. fanout distribution network gets more demanding and sophisticated as transceiver JESD204B Interface count increases. Another, and Figure 1: Channel-to-channel skew with parallel data buses The new JESD204B highless obvious, challenge is to speed digital interface shows collect the data from the various receivers and align promise of greatly simplifying the digital interconnects them with the proper timing relationship among between the data converters and the processor. Since each other. Misalignment of even a single sample the clock is embedded in the data stream, it eliminates across elements cannot be tolerated. The traditional the setup and hold time issue at the receiver and digital interfaces, such as parallel LVDS (low-voltage the additional board space required for trace length 14 Electronic Military & Defense ■ www.vertmarkets.com/electronics