Electronic Military & Defense magazine was developed for engineers, program managers, project managers, and those involved in the design and development of electronic and electro-optic systems for military, defense, and aerospace applications.
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Technology matching. While the inherent 8b/10b encoding increases overhead by 20%, it also includes error detection and ensures DC balancing. This allows AC coupling between receiver and transmitter, and each end can be optimized for the most suitable common-mode voltage. The traditional LVDS interface works very reliably up to a data rate of ~1 Gbps. The JESD204B, on the other hand, accommodates interface rates up to 12.5 Gbps. Hence, the number of differential traces used for data transmission can Figure 2: Parallel versus JESD204B interface be vastly reduced. The result is a drastic board area savings, especially for multichannel data to the local multiframe clock (LMFC) edge. systems. A dual-channel 16-bit ADC with a DDR The system reference clock (SYSREF) in subclass 1 LVDS interface uses 17 differential pairs (16 data is a timing signal that aligns LMFCs across different and 1 clock) to transmit the data, while a JESD204B devices. This allows synchronization of multiple interface reduces it to merely five differential pairs (4 data converters as well as receiver and transmitter data and 1 synch). It even accommodates cases where devices. The initial SYSREF pulse also resets internal blocks, such as an input clock divider, to a preset condition, which ensures a known, deterministic latency independent of PVT variation. Timing skew due to JESD204B trace length mismatch across ADCs is absorbed with elastic buffers in the receiver. However, one challenge still remains. This is the time alignment of the sampling clocks and SYSREF signals that are distributed to the various data converters. Their trace lengths need to be matched so that the LMFCs are latched in and registered at the sample instant in time. Clock jitter cleaners, which support subclass 1, also provide flexibility to add different amounts of delay to individual outputs in order to compensate for different trace lengths. Figure 3: JESD204B system with subclass 1 several "slower" ADCs can share one fast serializer/ deserializer (SerDes) lane for further board area, but also SerDes transceiver savings in the FPGA. For example, two ADCs sampling at 80 Msps can transmit the output data over one JESD204B SerDes link operating at 3.2 Gbps. The subclass 1 of the JESD204B standard enables simple alignment of standalone data converters by synchronizing transmission and reception of parallel 16 Electronic Military & Defense ■ www.vertmarkets.com/electronics Summary Performance requirements for radars will continue to increase, and the phased-array radar likely will play a key role. The JESD204B digital interface provides an easier way, compared to traditional interfaces, to synchronize the individual elements of very large, multichannel arrays. Devices equipped with the new JESD204B digital interface will meet the AC requirements in modern radar applications. Thomas Neu is a systems engineer for Texas Instrument's highspeed data converters group, where he provides applications support. He received his MSEE from Johns Hopkins University and can be reached at ti_tneu@list.ti.com.