Electronic Military & Defense magazine was developed for engineers, program managers, project managers, and those involved in the design and development of electronic and electro-optic systems for military, defense, and aerospace applications.
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Technology Electronic Military & Defense Annual Resource, 5th Edition 25 it takes to move data to the coprocessor becomes significant relative to the number of compute cycles to be performed, then there are diminishing returns to using the coprocessor, because the data movement serializes this effort. The second architecture that lends itself easily to an HLL design approach is the processing of data streams from cam- eras and sensors. This is a bump-in-the-wire view (Figure 1) where processing is done at various stream locations. Amdahl's law doesn't apply in this case because the parallelization is implicit, because increasing the image frame size only requires adding more parallel resources to the FPGA fabric. The "bump" lends itself to HLL. The ends of the plumbing (I/O) lend themselves to custom HDL work, unless there is a connection standard or the I/O is abstracted via a board support package (BSP). How Design Goals And Type Drive Architectural And Tuning Decisions In the real world, FPGAs often bog down if they have to access anything off chip. The I/O and integration can block a project. Over the years, we've found that our engineers spend as much time on "plumbing" and testing as they do on design. What we mean by "plumbing" is the task of getting all the board hardware hooked up and communicating at speed. This is par- ticularly problematic in the (relatively) low-volume FPGA boards. Impulse provides a fair number of BSPs, which generally are cost-justified if the plat- form is to be used for more than one project; they enable software develop- ers to write in HLL and access board hardware features, such as memory and I/O. Architecture And Partitioning Architecture and partitioning entails managing on-chip, on-board, and host resources to minimize I/O and to allo- cate ideal resources for various func- tions. Secondarily, "libraries" that are more like functional blocks (e.g., basic linear algebra subroutines, or BLAS) optimize only when melded with pri- mary code — a fine tuning issue that isn't "in the manual." Sometimes, the fine tuning bites you in other ways. At the extremes, it is akin to "hot rodding," wherein systems are supposed to run at their theoreti- cal max but don't due to system con- straints. For example, a few years ago, we encountered a board in which the memory speed spec was for the chip running solo. When we queried the board manufacturer, they admitted it had never been verified on a board and, ultimately, was not achievable. A related architectural question involves the locus of pro- cessing. Using a camera as an example, shifting the process- ing to the camera unloads the communication network but increases the cost of the camera. It's a complex decision. For stereoscopic unmanned aerial vehicles (UAVs), there is incentive to process information on board the UAV and then (YDQVFDSVDUHDOZD\VVSHFLÀHGLQKXQGUHGVRIGHIHQVHFULWLFDODLUPLVVLRQVEHFDXVH WKH\DUHDOZD\VPRUHHQHUJ\GHQVHDOZD\VUHDG\DQGDOZD\VUHOLDEOH (YDQVFDSVKDYHPRUHLQWKHLUKHUPHWLFWDQWDOXPSDFNDJHVWKDQDQ\RWKHUFDSDFLWRU 7KH\ZHUHGHOLYHUHGWRRYHUDHURVSDFHDQGGHIHQVHFXVWRPHUVODVW\HDU (YDQVFDSVWKHFDSDFLWRUVRIFKRLFHIRUSKDVHGDUUD\UDGDUODVHUWDUJHWLQJDYLRQLFV GLVSOD\VFRPPXQLFDWLRQVZHDSRQVV\VWHPV-756VRIWZDUHGHÀQHGUDGLRVSDFH V\VWHPVDQGSRZHUKROGXS$OZD\V 10V to 125V Low ESR >100 Amp Discharge Unlimited Cycle Life High Shock and Vibe 5 Million Hour MTBF - 55°C to 125°C Operation w w w. e v a n s c a p . c o m for specs and pricing Since 1996 EVANSCAPS ALWAYS The Evans Capacitor Co. %R\G$YHQXH (DVW3URYLGHQFH5,86$ )$;FKDVG#HYDQVFDSFRP